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data sheet powerpc 401gf 32-bit risc embedded controller features ? powerpc ? risc cpu core and instruction set architecture ? pipelined cpu core runs at up to 4x the external bus clock rate ? separate instruction cache and write-back/ write-through data cache, both two-way set- associative ? multiplexed external bus ? configurable interfaces to memory and peripherals: Cdevice-paced wait states C8-,16-, or 32-bit bus widths Cprogrammable hold states ? flexible interface to external bus masters ? integrated power management and clock gen- erator ? big-endian or little-endian device attachment ? hardware support for unaligned accesses ? thirty-two 32-bit general purpose registers applications ? set-top boxes ? consumer electronics and video games ? telecommunications and networking ? office automation (printers, copiers, fax) ? personal digital assistants (pda) specifications ? cpu core frequency to 50 mhz, i/os to 25 mhz ? interfaces to both 3v and 5v technologies ? low-power 3.3v operation with doze/nap/ sleep modes ? low-cost 80-lead tqfp package ? 0.5 m m triple-level-metal cmos overview the 401gf risc controller consists of a pipelined cpu core, data cache unit (dcu), instruction cache unit (icu), memory management unit (mmu), bus control unit (bcu), asynchronous interrupt controller, and jtag debug port. the internal 2kb instruction cache and 1kb data cache reduce overhead for data transfers to or from external memory. each cache unit consists of a data array and a tag array, and the mmu is provided for cache management and addressing. the cpu core consists of general purpose regis- ters (gpr), special purpose registers (spr), alu, barrel shifter, and the control logic required to manage data flow and instruction execution within the cpu core. risc cpu core cache unit instruction cache unit data bus control unit bus controls address/ timers: pit, fit, 64-bit base data bus 1x-4x core clocking real-mode mmu power mgmt gen clock jtag port interrupt controller memclk osc thirty-two 32-bit gprs
ibm powerpc 401gf 2 the cpu core handles instruction decoding and execution. the instruction cache unit passes instructions to the queue in the cpu core or, in the event of a cache miss, requests a fetch from external memory through the bus control unit. general purpose registers data transfers to and from the cpu core are handled through the bank of 32 gprs, each 32 bits wide. load and store instructions move data operands between the gprs and the data cache unit, except in the cases of noncacheable data or cache misses. in such cases the dcu passes the address for the data read or write to the bcu. when noncacheable operands are being transferred, data can pass directly between the cpu core and the bcu, which interfaces to the external memory being accessed. special purpose registers special purpose registers are used to control debug facilities, timers, interrupts, memory cacheability, and other architected processor resources. sprs are accessed using move to/ from special purpose register (mtspr/mfspr) instructions, which move operands between gprs and sprs. supervisory programs can write the appropriate sprs to configure the operating and interface modes of the cpu core. the condition register (cr) and machine state register (msr) are written by internal control logic with program execution status and machine state, respectively. fixed-point arithmetic exception status is available from the exception register (xer). device control registers device control registers (dcr) are used to manage i/o interfaces. dcrs are accessed using move to/from device control register (mtdcr/mfdcr) instructions, which move operands between gprs and dcrs. instruction set table 1 summarizes the 401gf instruction set by categories of operations. when the requisite data and instructions are available in cache, the cpu core executes most instructions in a single cycle, with the exception of multiply, divide, and storage instructions. bus control unit the bcu controls address output and data transfers on the multiplexed external bus, b0:31. to enhance data transfer bandwidth, the bcu supports both four-beat burst access and continuous burst access, up to 16 transfers. table 1. 401gf instructions by category category base instructions data movement load, store arithmetic / logical add, subtract, negate, multiply, divide, and, or, xor, nand, nor, xnor, sign extension, count leading zeros comparison compare, compare logical, compare immediate branch branch, branch conditional condition condition register logical rotate/shift rotate, rotate and mask, shift left, shift right cache control invalidate, touch, zero, flush, store interrupt control write to external interrupt enable bit, move to/from machine state register, return from interrupt, return from critical interrupt processor management system call, synchronize, move to/from device control registers, move to/ from special purpose registers
ibm powerpc 401gf 3 all 401gf external bus operations are synchronous to the memclk output, simplifying control logic for external memory attached to the bus. the external bus interface can be programmed to operate at 1x, 1/2x, 1/3x or 1/4x the internal clock speed. bus width is programmable to support attachment to 8-, 16-, and 32-bit memory and peripherals. further details of peripheral attachment are given in "connecting to the 401gf bus," on page 12. memory addressing regions the 401gf can address an effective range of four gigabytes, mapped to eight 512mb regions. region attributes such as hold time, bus width, burst mode, and cache line mode (sequential/ target word first) are controlled by the eight bus region control registers (brcr). wait states are device-paced so the bus interface can be used with i/o devices of varying speeds. cacheability with respect to the instruction and data caches is programmed via the instruction and data cache control registers, respectively. instruction cache unit the instruction cache unit (icu) is a two-way set- associative 2kb cache memory unit. the icu is organized as 64 sets of 2 lines, each line containing 16 bytes. the cache can send one cached instruction per cycle to the cpu core. the instruction queue can buffer two prefetched instructions, in addition to the instruction being decoded and the instruction currently being executed. a separate bypass path is available to handle cache-inhibited instructions and to improve performance during line fill operations. data cache unit the data cache unit is provided to minimize the access time of frequently used data items in external memory. the 1kb cache is organized as a two-way set associative cache. there are 32 sets of 2 lines, each line containing 16 bytes of data. the cache features byte-writeability to improve the performance of byte and halfword store operations. cache operations are performed using write- back or write-through strategy, as programmed in the data cache write-through register. a write- back cache only updates locations in external memory that corresponds to changed locations in the cache. data is flushed from the cache to external memory whenever changed data needs to be removed from the cache to make room for other data. write-through cache operation is supported as a programmable cache management option. the data cache may be disabled for a memory region via control bits in the data cache control register. a separate bypass path is available to handle cache-inhibited data operations and to improve performance during line fill operations. cache flushing and filling are triggered by load, store, and cache control instructions executed by the processor. exception handling the 401gf contains a unique dual-level interrupt structure, which is specific to the ibm powerpc 400series family. this interrupt structure allows for a typical latency of 3 cycles to critical system interrupts as well as robust debug capability, even for first level interrupt handlers. exceptions are generated by interrupts from external peripherals, instructions, the internal timer facility, debug events or error conditions. two external interrupt signals are provided on the 401gf: one critical and one general-purpose. the 401gf processes exceptions as either, criti- cal or non-critical. four exceptions are defined as critical: machine check exceptions, debug excep- tions, exceptions caused by an active level on the critical interrupt pin, and the first time-out from the watchdog timer.all other exceptions are non- critical. each class of exception has its own pair of save/ restore registers to hold the status and instruc- tion address of the routine which was running at the time of the exception. this state is automati- cally restored upon execution of a return-from- interrupt (rfi) or return-from-critical-interrupt (rfci) instruction.
ibm powerpc 401gf 4 timers the 401gf contains four timer functions: a time base, a programmable interval timer (pit), a fixed interval timer (fit), and a watchdog timer. the time base is a 64-bit counter incremented by an internal signal equal to the cpu core clock rate. no interrupts are generated when the time base rolls over. the programmable interval timer is a 32-bit register that is decremented at the same rate as the time base is incremented. the user preloads the pit register with a value to create the desired delay. when the register is decremented to zero, the timer stops decrementing, a bit is set in the timer status register (tsr), and a pit interrupt is generated. optionally, the pit can be programmed to reload automatically the last value written to the pit register, after which the pit begins decrementing again.the timer control register (tcr) contains the interrupt enable for the pit interrupt. the fixed interval timer generates periodic interrupts based on selected bits in the time base. users may select one of four intervals for the timer period by setting the correct bits in the tcr. when the selected bit in the time base changes from 0 to 1, a bit is set in the tsr and a fit interrupt is generated. the fit interrupt enable is contained in the tcr. the watchdog timer generates a periodic interrupt based on selected bits in the time base. users may select one of four time periods for the interval and the type of reset generated if the watchdog timer expires twice without an intervening clear from software. clock generation and power management the 401gf clock unit integrates clock generation and power management. the clock unit uses a crystal or oscillator input as a reference, generating both the internal clock signal used by the cpu core and the memclk output from the 401gf. duty cycle correction is performed on the crystal or oscillator reference input, as needed. the cpu core can operate with a clock rate up to four times that of the external bus, up to a maximum frequency of 50 mhz and a maximum bus frequency of 25 mhz. the clock unit also provides sleep mode management, reducing standby power consumption when programmed to invoke the three sleep modes (doze, nap, and sleep) available on the 401gf. jtag port the jtag port has been enhanced to allow it to be used as a debug port. through the jtag test access port, debug software on a workstation can single-step the processor and interrogate internal processor state to facilitate software debugging. the standard jtag boundary-scan register allows testing of circuitry external to the chip, primarily the board interconnect. alternatively, the jtag bypass register can be selected when no other test data register needs to be accessed during a board-level test operation. p/n code notes: 1. the dash number indicates the speed version (max- imum internal clock rate). 2. the characters in the dash number indicate package type (m), revision level (c), maximum inter- nal cpu core clock rate (mhz), commercial version (c), ratio of cpu core speed to external bus clock rate (2:1). for availability of 401gf versions operating at faster cpu core frequencies, please contact your ibm microelectronics sales representative. table 2. ppc401gf part number mhz (cpu core) part number 50 PPC401GF-MC50C2
ibm powerpc 401gf 5 logic symbol signals in brackets are multiplexed. bootxtal xtal1 holdreq holdack busreq extint memclk bootw critint buserror reset ready abus28:29 ale be0 [a31] be3 blast w/r tck tms tdi tdo b0 b31 halt ? ? ? buswidth0:1 bootclkspd multiplexed address and data bus external master interrupts jtag bus controls be1 [a30] be2 te s t a 401gf risc controller xtal2 init/reset controls controls
ibm powerpc 401gf 6 pin functional descriptions active-low signals are shown with overbars: be0 . multiplexed signals are alphabetized under the first (unmultiplexed) signal names on the same pins: be0 [a31]. the 401gf logic symbol above shows all signals arranged by functional groups. table 3. pin description nomenclature symbol description i input pin only o output pin only i/o pin can be either an input or output - pin must be connected as described. s(...) synchronous. inputs must meet setup and hold times relative to memclk for proper operation. s(e) edge sensitive s(l) level sensitive t(...) synchronous to tck. t(e) edge sensitive input t(l) level sensitive input a(...) asynchronous. inputs may be asynchronous relative to the memclk a(e) edge sensitive input a(l) level sensitive input r(...) while the processors reset pin is asserted, the pin: r(1) is driven high r(0) is driven low r(q) is a valid output r(x) is driven to unknown state r(z) is placed in high impedance h(...) while the processor is in the hold state, the pin: h(1) is driven high h(0) is driven low h(q) maintains previous state or continues to be a valid output h(z) floats
ibm powerpc 401gf 7 table 4. 401gf signal descriptions signal name pin i/o type function abus28 77 o r(z) h(z) address bits a28:29. abus28:29 output a partial unmultiplexed word address during the address state. the partial word address is incremented, with each assertion of ready , during burst transfers. abus29 78 ale 76 o r(0) h(z) address latch enable. the 401gf asserts this signal high at the beginning of the cycle when an address is output on the multiplexed bus. the signal goes inactive before the beginning of the data state. for an early implementation of the 401gf (part no. ppc401gf- ma50c2), the polarity of the ale signal was reversed and this signal was active low (ale ). for all other ppc401gf chips, ale is active high. b0 39 i/o s(l) r(z) h(z) multiplexed bus bit 0. this bus, b0:31, carries 32-bit physical addresses and 8-, 16-, and 32-bit data to and from memory. during the wait/data state, read or write data is present on one or more contiguous bytes. during write operations, unused pins continue to drive address; during read operations, unused pins are hi-z. the determinate values are also driven on the bus during the idle state. b1 38 i/o multiplexed bus bit 1 b2 37 i/o multiplexed bus bit 2 b3 36 i/o multiplexed bus bit 3 b4 35 i/o s(l) r(z) h(z) multiplexed bus bit 4. depending on burst mode configuration, transfer size information is output on b6:7 (brcr n [mb] = 0) for a four-beat burst, or on b4:7 (brcr n [mb] = 1) for continuous burst (up to 16 transfers). b5 34 i/o multiplexed bus bit 5. see description of b4 above. b6 33 i/o multiplexed bus bit 6. see description of b4 above. b7 29 i/o multiplexed bus bit 7. see description of b4 above. b8 49 i/o multiplexed bus bit 8 b9 48 i/o multiplexed bus bit 9 b10 47 i/o multiplexed bus bit 10 b11 46 i/o multiplexed bus bit 11 b12 45 i/o multiplexed bus bit 12 b13 42 i/o multiplexed bus bit 13 b14 41 i/o multiplexed bus bit 14 b15 40 i/o multiplexed bus bit 15 b16 61 i/o multiplexed bus bit 16
ibm powerpc 401gf 8 b17 60 i/o multiplexed bus bit 17 b18 59 i/o multiplexed bus bit 18 b19 56 i/o multiplexed bus bit 19 b20 55 i/o multiplexed bus bit 20 b21 54 i/o multiplexed bus bit 21 b22 53 i/o multiplexed bus bit 22 b23 52 i/o multiplexed bus bit 23 b24 72 i/o multiplexed bus bit 24 b25 68 i/o multiplexed bus bit 25 b26 67 i/o multiplexed bus bit 26 b27 66 i/o multiplexed bus bit 27 b28 65 i/o multiplexed bus bit 28 b29 64 i/o multiplexed bus bit 29 b30 63 i/o multiplexed bus bit 30 b31 62 i/o multiplexed bus bit 31 be0 [a31] 24 o r(1) h(z) byte enable 0[address 31]. be0:3 select which (of up to four) bytes on the bus participate in the current bus access. byte enable encoding depends on the bus width of the memory region accessed. the 401gf asserts byte enables during the address state. for unaligned burst transfers, these signals switch with each assertion of ready . be1 [a30] 25 o byte enable 1[address 30] be2 27 o byte enable 2 be3 28 o byte enable 3 table 4. 401gf signal descriptions (continued) signal name pin i/o type function be0 be1 be2 be3 32-bit bus accesses enables b0:7 enables b8:15 enables b16:23 enables b24:31 16-bit bus accesses enables b0:7 becomes addr a30 unused (high) enables b8:15 8-bit bus accesses becomes addr a31 becomes addr a30 unused (high) unused (high)
ibm powerpc 401gf 9 blast 21 o r(1) h(z) burst last. indicates the last transfer of a memory access, whether burst or nonburst. blast stays active as long as the ready signal is not asserted to introduce wait states on the external bus. blast goes inactive when the last transfer of an external bus transaction is done. bootclkspd 19 i s(l) the boot clock speed pin determines the internal clock speed and the bus clock speed. bootxtal 7 i s(l) boot crystal. this pin is for internal use only and should always be fixed high. bootw 9 i s(l) boot-up rom width select. bootw is sampled before and after the reset pin is active to determine the width of the boot-up rom. if this pin is tied to logic 0 when sampled on reset, an 8-bit boot width is assumed. if bootw is tied to logic 1, a 32-bit boot width is assumed. for 16-bit boot widths, this pin should be tied to the reset pin. buserror 13 i s(l) bus error input. a logic 0 input to the buserror pin by an external device signals to the 401gf that an error occurred on the bus transaction. buserror is only sampled when ready is asserted. busreq 22 o r(q) h(q) bus request. while holdack is active, busreq is active when the 401gf has a bus operation pending and needs to regain control of the bus. busreq is also active during bus operations. buswidth0 79 o r(z) h(z) buswidth0:1 indicates the width of a bus transaction on the 401gf external multiplexed bus: 00 = 8 bit, 01 = 16 bit, 10 = 32 bit, 11 = reserved. buswidth1 80 critint 15 i a(l) critical interrupt. critint is a critical interrupt input to the 401gf and users may program the polarity to be active high or active low. the iocr contains the bit necessary to program the polarity. extint 14 i a(l) external interrupt. extint is an interrupt input to the 401gf and users may program the polarity to be active high or active low. the iocr contains the bit necessary to program the polarity. table 4. 401gf signal descriptions (continued) signal name pin i/o type function bootclkspd internal clock memclk 0 1x of input clock 1x of internal clock 1 1/4x of input clock 1/4x of internal clock
ibm powerpc 401gf 10 gnd 10 ground. all ground pins must be used. 30 ground. all ground pins must be used. 32 ground. all ground pins must be used. 43 ground. all ground pins must be used. 50 ground. all ground pins must be used. 58 ground. all ground pins must be used. 69 ground. all ground pins must be used. 71 ground. all ground pins must be used. 75 ground. all ground pins must be used. halt 16 i, a(l) halt from external debugger, active low. holdack 2 o r(q) h(1) hold acknowledge. holdack outputs a logic 1 when the 401gf relinquishes its external bus to an external bus master. the external bus master uses the holdreq pin to request use of the 401gf bus. holdreq 11 i s(l) hold request. external bus masters can request the 401gf bus by placing a logic1 on this pin. when the 401gf holdack pin is logic 1, the 401gf has relinquished its external bus to the external master. the external bus master relinquishes the bus to the 401gf by deasserting holdreq. the 401gf then deasserts holdack during the following cycle. memclk 5 o r(q) h(q) memory clock. clock output from the internal 401gf clock generator. memclk is a clock output at the bus frequency. the bus can be configured to run at 1x, 1/2x, 1/3x or 1/4x the internal clock frequency. see memclk termination on page 16. ready 12 i s(l) ready. ready inserts externally generated (device-paced) wait states into bus transactions. ready indicates to the 401gf that data on the external bus can be sampled or removed. reset 73 i/o r(l) reset. as an input, the reset pin is driven low for 1 ms to perform a system reset. the reset signal, used as an output, can be driven by software or an external debug tool. when a system reset occurs, the reset pin outputs logic 0 for up to 2048 internal clock cycles. tck 18 i jtag test clock input. tck is the clock source for the 401gf test access port (tap). the maximum clock rate into the tck pin is one half of the processor memclk clock rate. tdi 8 i t(l) test data in. the tdi is used to input serial data into the tap. when the tap enables the use of the tdi pin, the tdi pin is sampled on the rising edge of tck and this data is input to the selected tap shift register. table 4. 401gf signal descriptions (continued) signal name pin i/o type function
ibm powerpc 401gf 11 tdo 1 o, r(z), h(q), t(l) test data output. tdo is used to transmit data from the 401gf tap. data from the selected tap shift register is shifted out on tdo. testa 20 i reserved for manufacturing test. tied low for normal operation. tms 17 i t(l) test mode select. the tms pin is sampled by the tap on the rising edge of tck. the tap state machine uses the tms pin to determine the mode in which the tap operates. v dd 6 power. all power pins must be connected to 3.3v supply. 26 power. all power pins must be connected to 3.3v supply. 31 power. all power pins must be connected to 3.3v supply. 44 power. all power pins must be connected to 3.3v supply. 51 power. all power pins must be connected to 3.3v supply. 57 power. all power pins must be connected to 3.3v supply. v dd 70 power. all power pins must be connected to 3.3v supply. 74 power. all power pins must be connected to 3.3v supply. w/r 23 o r(0) h(z) write/read . when the 401gf is bus master, w/r is an output (asserted only in address cycle) that is low when data is read from memory or a peripheral and high when data is written to memory or a peripheral. xtal1 3 crystal 1 input. xtal1 is the processor clock input. this pin can be connected to a oscillator or a crystal. xtal2 4 crystal 2 output. xtal2 is connected to the crystal. if xtal1 is connected to an oscillator instead of a crystal, this pin should be left unconnected. table 4. 401gf signal descriptions (continued) signal name pin i/o type function
ibm powerpc 401gf 12 connecting to the 401gf bus the figure below shows the byte and bit connections for attaching memory or peripheral devices to the 401gf external bus pins, b0:31. connect 8-bit devices to b0:7. for multibyte devices, connect the least significant bytes (lsb) and most significant bytes (msb) as indicated below, preserving normal ordering from most significant bit (msb) to least significant bit (lsb) within each byte. the 401gf external bus pins used for address output and data transfers are shown in the table below. address bits output by the 401gf are numbered a0:31, with a0 as the most significant bit (msb). connect be0 and be1 to the lsb and second lsb address inputs of an external 8-bit device. connect be1 to the second lsb address input of an external 16-bit device. connect abus28:29 to the fourth and third lsb address inputs of an external 32-bit device. word address output by 401gf: a0 (msb):7 a8:15 a16:23 a24:27 (see note) 401gf pins used to output address: b24 (msb):31 b16:23 b8:15 b0:3 note: address bits a28:31 are provided on pins abus28:29, be1 [a30], and be0 [a31], respectively. data bytes transferred: byte 0 byte 1 byte 2 byte 3 401gf pins used by data transfer: b0:7 b8:15 b16:23 b24:31 be0 be1 be2 be3 401gf bus control unit msb lsb b0 b7 b8 b15 b16 b23 b24 b31 ale msb lsb msb lsb msb lsb little endian peripherals address bus latch msb lsb be1 be2 big endian peripherals lsb msb lsb msb msb lsb msb lsb msb lsb msb lsb msb lsb msb lsb msb lsb msb lsb msb lsb msb lsb msb lsb msb lsb msb lsb msb lsb msb lsb msb lsb msb lsb msb lsb msb lsb msb lsb 401gf pins external devices be0 be3 be0 be3 be0 be3
ibm powerpc 401gf 13 tqfp mechanical drawing (top view) index mark 120 21 40 41 60 61 80 0.2 0.1 0.008 0.004 0.5 basic 0.02 dimensions: mm inches 1.7 max 0.067 0.05 min 0.002 0.5 0.2 0.02 0.008 0.125 0.05 0.005 0.002 0 - 10 see detail note: english dimensions are for reference only. 14 0.2 0.551 0.008 12 0.1 0.472 0.004
ibm powerpc 401gf 14 table 5. signals ordered by pin number pin signal names pin signal names pin signal names pin signal names 1tdo 21blast 41 b14 61 b16 2 holdack 22 busreq 42 b13 62 b31 3 xtal1 23 w/r 43 gnd 63 b30 4 xtal2 24 be0 [a31] 44 v dd 64 b29 5 memclk 25 be1 [a30] 45 b12 65 b28 6v dd 26 v dd 46 b11 66 b27 7 bootxtal 27 be2 47 b10 67 b26 8 tdi 28 be3 48 b9 68 b25 9 bootw 29 b7 49 b8 69 gnd 10 gnd 30 gnd 50 gnd 70 v dd 11 holdreq 31 v dd 51 v dd 71 gnd 12 ready 32 gnd 52 b23 72 b24 13 buserror 33 b6 53 b22 73 reset 14 extint 34 b5 54 b21 74 v dd 15 critint 35 b4 55 b20 75 gnd 16 halt 36 b3 56 b19 76 ale 17 tms 37 b2 57 v dd 77 abus28 18 tck 38 b1 58 gnd 78 abus29 19 bootclkspd 39 b0 59 b18 79 buswidth0 20 testa 40 b15 60 b17 80 buswidth1
ibm powerpc 401gf 15 package thermal specifications the 401gf is designed to operate within the case temperature range from 0c to 120c. thermal resistance values for the tqfp are shown in table 6: notes: 1. case temperature tm c is measured at top center of case surface with device soldered to circuit board. 2. tm a = tm c C p q ca , where tm a is ambient tem- perature. 3. tm cmax = tm jmax C p q jc , where tm jmax is maxi- mum junction temperature and p is power con- sumption. 4. the above assumes that the chip is mounted on a card with at least one signal and two power planes. electrical specifications absolute maximum ratings the absolute maximum ratings in table 7 below are stress ratings only. operation at or beyond these maximum ratings may cause permanent damage to the device. note: maximum input voltage applied to the xtal1 input pin must not exceed 3.47 v. operating conditions the 401gf can interface to either 3v or 5v technologies. the range for supply voltages is specified for five-percent margins relative to a nominal 3.3v power supply. device operation beyond the conditions specified in table 8 is not recommended. extended operation beyond the recommended conditions may affect device reliability: note: if used, a 3.3v oscillator should be placed as close as possible to the xtal1 input. power considerations power dissipation is determined by operating frequency, temperature, and supply voltage, as well as external source/sink current requirements. typical power dissipation for 25mhz external bus operation and 50mhz cpu core operation is estimated as 203 mw at tm c = 25 c, and v cc = 3.3 v, with an average 50pf capacitive load. estimated supply current as a function of frequency is shown in the figure, "memclk output derating curves," on page 22. derating curves are provided in the section, "output derating for capacitance and voltage," on page 22. recommended connections power and ground pins should all be connected to separate power and ground planes in the circuit board to which the 401gf is mounted. unused input pins must be tied inactive, either high or low. table 6. thermal resistance (c/watt) parameter airflow-ft/min (m/sec) 0 (0) 100 (0.51) 200 (1.02) q jc junction to case 222 q ca case to ambient (without heatsink) 37.2 31.6 29.8 table 7. 401gf maximum ratings parameter maximum rating supply voltage with respect to gnd -0.5v to +3.8v voltage on other pins with respect to gnd -0.5v to +5.25v (see note) case temperature under bias 0c to +120c storage temperature -65c to +150c table 8. operating conditions symbol parameter min max unit v dd supply voltage 3.14 3.47 v f xtal1 xtal1 input frequency 24.975 25.025 mhz input high time 14 ns input low time 14 tm c case tempera- ture under bias 0 +85 c
ibm powerpc 401gf 16 memclk termination when memclk alignment is enabled (iocr[mca] = 1), memclk must be terminated such that voltage spikes on the rising edge of memclk do not appear at the off-chip driver. these spikes are caused by impedance mismatches. impedance mismatches between the off-chip driver at memclk and external loading may result in reflections which distort the positive rising edge of memclk. the memclk off-chip driver has an output impedance of 10 ohms. connecting a crystal to the 401gf dc specifications table 9. 401gf dc characteristics symbol parameter min max units v il input low voltage gnd - 0.1 0.8 v v ih input high voltage 2.0 (note 4) 5.25 (note 2) v v ol output low voltage 0.4 v v oh output high voltage 2.0 3.47 v i oh output high current 2 ma i ol output low current 4 ma i li input leakage current 75 m a i lo output leakage current 10 m a i cc supply current (i cc max at f c of 25mhz) 1 90 ma attach a quartz crystal such as a seiko epson ma-506 or equivalent across the xtal1 input and the xtal2 output. locate the crystal within 1.2 cm (0.5 inch) of the 401gf pins to minimize stray capacitance that can affect c load capacitance and, in turn, oscillator frequency and stability. the expression at right can be used to determine the c load value. the figure at right shows details concerning the inclusion of resistors and load capacitors required with the crystal.typical values for load capacitors c1 and c2 are 5-10pf. typical values for resistor r1 are in the range of 1-5 megohms. series resistor r2 is determined by the value of c2 and the osc output resistance, 150-200 ohms. the q factor of the rc circuit should be in the range of 2 q 5, deriving q from the expressions below: r2 functions as a current limiting resistor to the crystal, and also as an oscillation stabilizer in the presence of perturbations induced by moisture, component variations, or other factors. q = r out + r2 x c2 where: r out = osc output resistance r2 = resistor value to derive x c2 = c2 capacitive reactance at osc frequency r2 = qx c2 - r out xtal1 xtal2 c load = c 1 c 2 c 1 + c 2 + c stray pin pin osc xtal r1 r2 c1 c2
ibm powerpc 401gf 17 notes: 1. i cc max is measured at t j = 85 c , worst-case recommended operating conditions for frequency and voltage as specified in "operating conditions," on page 15, and a capacitive load of 50 pf. 2. the maximum v ih level applied to the xtal1 input pin must not exceed 3.47 v. 3. the maximum v il level applied to the xtal1 input pin must not exceed 0.4 v. 4. for reset pin, v ih min is 2.2 v. notes: 1. power management control register. 2. memclk alignment. 3. based on tested samples exhibiting no i/o leakage. it is possible for some leakage to be present, but less than the maximum defined by the i/o leakage specification. in such cases, a small amount of power may be consumed. 4. the test conditions were 3.3v, 25 c, core:bus speed set to 1:1, with memclk driving a 25pf capacitive load. notes: 1. c out is specified as the load capacitance of a floating output in high impedance. ac specifications table 10. nominal sleep-mode power mode pmcr0 1 value description mca 2 power off on 1 00004000 awake: processor halted 41.79mw 47.73mw 2 10004000 timer doze: timers off 41.13mw 47.07mw 3 20004000 chip doze: chip clock off 35.89mw 41.83mw 4 30004000 timer and chip doze: timers and chip clock are off 30.54mw 36.48mw 5 40004000 nap: only the crystal oscillator is running 5.63mw 6 80004000 deep sleep: everything is off 0mw 3 table 11. 401gf i/o capacitance symbol parameter min max units c in input capacitance 5 pf c out output capacitance 1 7pf c i/o i/o pin capacitance 8 pf output pin c l c l = 50 pf for all signals clock timing and switching characteristics are specified in accordance with recommended operating conditions in table 8. ac specifications are characterized at voltage 3.14v v dd 3.5v and junction tempera- ture 0c t j 85c with the 50pf test load shown in the figure at right. derating of outputs for capacitive loading is shown in the figure "output derating for capacitance and voltage," on page 22.
ibm powerpc 401gf 18 memclk timing notes: 1. worst-case clock edge stability is accounted for in the ac i/o timing specification. 2. rise and fall times measured between 0.8v and 2.0v. assumes 50 pf capacitive load, v dd = 3.14v and t j = 85c table 12. 401gf memclk timing symbol parameter 401gf-mc50c2 units min max f c memclk clock output frequency 24.975 25.025 mhz t c memclk clock period 39.96 40.04 ns t cs clock edge stability 1 0.8 ns t ch clock output high time 16 ns t cl clock output low time 16 ns t cr clock output rise time 2 0.5 2.5 ns t cf clock output fall time 2 0.5 2.5 ns t cr t cf t cl t ch t c 2.0v 1.5v 0.8v
ibm powerpc 401gf 19 input setup and hold waveform notes: 1. timings are guaranteed by design and characterization. 2. these i/o timings are valid when the input clock = 25mhz 0.1%, the chip is in 2x:1/2x or 1x:1x mode and mem- clk alignment is enabled. when memclk is not 25mhz, memclk alignment should be disabled and the i/o timings should be adjusted by the constants obtained from the "memclk output derating curves," on page 22. when memclk alignment is off, new input setup times (t is ) are derived by adding constant k1 to the setup times in table 13. t is(compoff) = t is + k1. when memclk alignment is off, new input hold times (t ih ) are derived by subtracting constant k2 from the input hold times listed in table 13. t ih(compoff) = t ih - k2. 3. memclk must be terminated if memclk alignment is enabled (iocr[mca]=1). see memclk termination on page 16. table 13. 401gf synchronous input timings symbol parameter 401gf-mc50c2 units min max t is input setup: t is1 t is2 t is3 t is4 b0:31 buserror holdreq ready 5 8 5.5 9 ns t ih input hold: t ih1 t ih2 t ih3 t ih4 b0:31 buserror holdreq ready 1 1 1 1 ns t r ,t f input rise/fall time 0.5 2.5 ns valid t is t ih 1.5v 1.5v min min inputs memclk 1.5v 1.5v 1.5v
ibm powerpc 401gf 20 notes: 1. during a system-initiated reset, reset must be taken low for a minimum of one millisecond. 2. external interrupts must be held active until software interrupt handling begins. 3. the bootw input has a maximum rise time requirement of 10 ns when it is tied to reset . 4. input hold times are measured at 3.47v and t j = 10 c. 5. these i/o timings are valid when the input clock = 25mhz 0.1%, the chip is in 2x:1/2x or 1x:1x mode and mem- clk alignment is enabled. when memclk is not 25mhz, memclk alignment should be disabled and the i/o timings should be adjusted by the constants obtained from the "memclk output derating curves," on page 22. when memclk alignment is off, new input setup times (t is ) are derived by adding constant k1 to the setup times in table 14. t is(compoff) = t is + k1. when memclk alignment is off, new input hold times (t ih ) are derived by subtracting constant k2 from the input hold times listed in table 14. t ih(compoff) = t ih - k2. 6. memclk must be terminated if memclk alignment is enabled (iocr[mca]=1). see memclk termination on page 16. 7. the setup times provided for the asynchronous inputs do not need to be met. if met, two synchronization cycles are used instead of three cycles output delay and float timing waveform table 14. 401gf asynchronous input timings symbol parameter 401gf-mc50c2 units min max t is input setup time t is10 t is11 t is12 t is13 critint extint halt reset 8 8 4 20 ns t ih input hold time t ih10 t ih11 t ih12 t ih13 critint extint halt reset note 2 note 2 note 2 note 3 ns valid t ov t oh 1.5v 1.5v 1.5v min outputs memclk outputs t of min max max 1.5v 1.5v 1.5v
ibm powerpc 401gf 21 notes: 1. ale t ohmin is with reference to the falling edge of mem clock. 2. refer to the powerpc 401gf users manual for detailed information on processor reset and initialization. 3. output times are measured with a standard 50pf capacitive load, unless otherwise noted. output hold times are measured at 3.47v and t j = 10 c. 4. these i/o timings are valid when the input clock = 25mhz 0.1%, the chip is in 2x:1/2x or 1x:1x mode and mem- clk alignment enabled. when memclk is not 25mhz, memclk alignment should be disabled and the i/o timings should be adjusted by the constants obtained from the "memclk output derating curves," on page 22. when memclk alignment is off, new output valid times (t ov ) and new maximum output float times (t ofmax ) are derived by subtracting constant k2 from the values listed in table 15. t ov(compoff) = t ov - k1. t ofmax(compoff) = t ofmax - k1. when memclk alignment is off new output hold times (t oh ) and new minimum output float times (t ofmin ) are derived by subtracting constant k1 from the values listed in table 15. t oh(compoff) = t oh - k2. t ofmin(compoff) = t ofmin - k2. 5. memclk must be terminated if memclk alignment is enabled (iocr[mca]=1). see memclk termination on page 16. 6. output hold and float times are guaranteed by design and not tested. 7. t ofmax also represents the amount of time it takes for the drivers to come out of hi-z state. t ofmin is the amount of hold time the drivers provide when going into the hi-z state. table 15. 401gf synchronous output timings symbol parameter 401gf-mc50c2 units t oh , t ov output hold, output valid time t oh1 , t ov1 t oh2 , t ov2 t oh3 , t ov3 t oh4 , t ov4 t oh5 , t ov5 t oh6 , t ov6 t oh7 , t ov7 t oh8 , t ov8 t oh9 , t ov9 t oh10 , t ov10 t oh11 , t ov11 t oh12 , t ov12 abus28:29 b0:31 ale be0[a31] be1[a30] be2:3 blast busreq buswidth0:1 holdack reset w/r t ohmin 1 1 1 1 1 1 1 1 1 1 1 1 t ovmax 10 12 10 11 11 11 11 11 11 11 12 10 ns t of output float time t of1 t of2 t of3 t of4 t of5 t of6 t of7 t of8 t of9 t of10 abus28:29 b0:31 ale be0[a31] be1[a30] be2:3 blast buswidth0:1 reset w/r t ofmin 1 1 1 1 1 1 1 1 1 1 t ofmax 10 10 10 10 10 10 10 11 9 10 ns
ibm powerpc 401gf 22 memclk output derating curves note: 1. k1 and k2 are independent of loading when using series termination. see memclk termination on page 16. output derating for capacitance and voltage k1 = d output delay (ns) 2 c l (pf) temp = 85c 20 voltage = 3.1v test conditions: 40 60 80 u n t e r mi n a t e d 4 3 5 memclk skew curve (worst case) terminated 100 120 140 6 7 k2 = d output delay (ns) 1 c l (pf) temp = 0c 20 voltage = 3.5v test conditions: 40 60 80 u n t e r m i n a t e d 0 memclk skew curve (best case) terminated 100 120 140 2 0 50 100 150 0 C2 +4 +2 d output delay (ns) c l (pf) tp zl d c = 0.09c l - 1ns derating equations for output delays: 1. d tp lh (c l , v) = tp lh d c + tp lh d v 2. d tp hl (c l , v) = tp hl d c + tp hl d v 3 . d tp zl5v (c l , v) = tp zl d c + tp hl d v (from 5.5v) 4. t r (c l ) = 1.5ns + tp r d c 5. t f (c l ) = 2.1ns + tp f d c derating equations for output rise and fall times: test conditions: v t = 0.8v to 2v at t j = 85c 0 +2 050 100 150 +4 C2 d output transition (ns) c l (pf) tp r d c tp f d c +6 +8 +10 +12 tp hl d c = 0.04c l - 1.9ns tp lh d c = 0.03c l - 1.4ns
ibm powerpc 401gf 23 output propagation delay derating vs. output voltage level reset and holdack the following table summarizes the states of signals on output pins when reset or holdack is active. note: 1. signal may be active while holdack is asserted, depending on the operation being performed by the 401gf. table 16. signal states during reset or hold acknowledge signal names state when reset active state when holdack active abus28:29 b0:31 ale be0 [a31] floating floating inactive (low) inactive (high) floating floating floating floating be1 [a30] be3:2 blast busreq inactive (high) inactive (high) inactive (high) valid output floating floating floating operable (see note 1) buswidth0:1 holdack memclk reset floating valid output inactive (high) floating unless initiating system reset floating active operable (see note 1) floating unless initiating system reset tdo w/r floating read (low) floating floating 1.5 3 0 0 +2 +4 +6 tp lh d v (c l = 25 pf) tp lh d v (c l = 50pf) tp lh d v (c l = 100 pf) v out (v) note: test condition t j = 85c d output delay (ns) tp hl d v (c l = 100 pf) tp hl d v (c l = 50pf) tp hl d v (c l = 25 pf)
ibm powerpc 401gf 24 bus waveforms the waveforms in this section represent external bus operations and external master operations. nonburst read and write word transfer (no wait state, one recovery state, 32-bit bus) cycles in this diagram are labeled according to the following key: a = address cycle i = idle cycle r = recovery cycle d = data cycle 0 1 2 3 4 5 6 7 8 9 memclk blast ready w/r abus28:29 be0 [a31] buswidth0:1 ale 10 b0:31 be1 [a30] be2 be3 addr addr data out din 10 adr i i adr i i
ibm powerpc 401gf 25 burst read and write line transfer (no wait state, one recovery state) cycles in this diagram are labeled according to the following key: a = address cycle d = data cycle r = recovery cycle memclk 01 addr addr d3 din 10 din out d0 out d1 out d2 out (00 or 01) or (10 or 11) 00 01 10 11 blast ready w/r abus28:29 be0 [a31] buswidth0:1 ale b0:31 be1 [a30] be2 be3 0 1 2 3 4 5 6 7 8 9 addraddddr
ibm powerpc 401gf 26 four beat burst read and write transfer (no wait state, one recovery state, 8-bit bus) cycles in this diagram are labeled according to the following key: a = address cycle d = data cycle r = recovery cycle 10 0 1 2 3 4 5 6 7 8 9 memclk 00 addr addr d3 din 00 din out d0 d1 d2 00 or 01 or 10 or 11 00 or 01 or 10 or 11 blast ready w/r abus28:29 be0 [a31] buswidth0:1 ale b0:31 be1 [a30] be2 be3 din din 11 out out out d addddraddd r
ibm powerpc 401gf 27 continuous burst read transfer (no wait state, one recovery state, 8-bit bus) cycles in this diagram are labeled according to the following key: a = address cycle i = idle cycle r = recovery cycle d = data cycle 0 1 2 3 4 5 6 7 8 9 memclk 00 addr din 00 00 01 blast ready w/r abus28:29 be0 [a31] buswidth0:1 ale b0:31 be1 [a30] be2 be3 10 10 11 12 13 14 15 16 17 din din din din din din din din din din din din din din din 11 18 addddddddddddddddr i
ibm powerpc 401gf 28 burst write transfer (2-1-1-1 wait state, one recovery state, 32-bit bus) cycles in this diagram are labeled according to the following key: a = address cycle i = idle cycle w = wait cycle d = data cycle r = recovery cycle memclk 10 addr 00 01 10 11 data0 out data1 out data2 out data3 out blast ready w/r abus28:29 be0 [a31] buswidth0:1 ale b0:31 be1 [a30] be2 be3 awwdwdwdwd r i 0 1 2 3 4 5 6 7 8 9 10 11
ibm powerpc 401gf 29 burst read/write unaligned hw transfer (1-0 wait state; 2 recovery state; 16-bit bus) cycles in this diagram are labeled according to the following key: a = address cycle r = recovery cycle w = wait cycle d = data cycle 0 1 2 3 4 5 6 7 8 10 memclk 01 addr addr din 01 din 00 or 01 or 10 or 11 00 or 01 or 10 or 11 d0 out blast ready w/r abus28:29 be0 [a31] buswidth0:1 ale b0:31 be1 [a30] be2 be3 9 d1 out awddrrawd r d
ibm powerpc 401gf 30 3-byte transfer bus request starting at word address (1-0 wait state, 1 recovery state) cycles in this diagram are labeled according to the following key: a = address cycle i = idle cycle w = wait cycle d = data cycle r = recovery cycle 0 1 2 3 4 5 6 7 8 memclk 01 addr din 10 din 00 or 01 or 10 or 11 00 or 01 or 10 or 11 blast ready w/r abus28:29 be0 [a31] buswidth0:1 ale b0:31 be1 [a30] be2 be3 addr din aw d d r a w d r i 9
ibm powerpc 401gf 31 unaligned transfer read bus request, cross word boundary (no wait state, 1 recovery state, 32-bit bus) cycles in this diagram are labeled according to the following key: a = address cycle i = idle cycle r = recovery cycle d = data cycle 0 1 2 3 4 5 6 7 8 9 memclk 10 addr din 10 00 01 blast ready w/r abus28:29 be0 [a31] buswidth0:1 ale b0:31 be1 [a30] be2 be3 addr din addr din 10 adradradr i
ibm powerpc 401gf 32 external master protocol cycles in these diagrams are labeled according to the following key: wake-up timing wake-up events: external interrupt, critical interrupt, hold, reset, halt a = address cycle h = external master hold r = recovery cycle d = data cycle i = idle cycle w = wait cycle memclk output controls bcu data holdreq holdack busreq bcu data r h h h i a w/d 0 1 2 3 4 5 6 7 8 9 memclk wake-up bus idle b0:31 earliest event addr address cycle iiiiiiii 1x cpu core clocking ? 1 ms osc wake-up valid 12345678
ibm powerpc 401gf 33 power-on reset cycles in this diagram are labeled according to the following key: i = idle cycle 0 1 2 3 4 memclk blast reset w/r abus28:29 be0 [a31] buswidth0:1 ale b0:31 be1 [a30] be2 be3 ? 1 ms osc wake-up i i iii
ibm powerpc 401gf 34
ibm powerpc 401gf 35
11.19.97 ? copyright ibm corporation 1996,8. all rights reserved. printed in the usa on recycled paper. 2-98 ibm microelectronics, powerpc, powerpc architecture, and 401gf are trademarks, ibm and the ibm logo are registered trademarks of ibm corporation. this document may contain preliminary information and is subject to change by ibm without notice. ibm assumes no responsibility of liability for any use of the information contained herein. nothing in this docu- ment shall operate as an express or implied license or indemnity under the intellectual property rights of ibm or third parties. the products described in this document are not intended for use in implantation or other direct life support applications where malfunction may result in direct physical harm or injury to persons. no warranties of any kind, including but not limited to the implied warran- ties of merchantability or fitness for a particular purpose, are offered in this document. ibm microelectronics division 1580 route 52, bldg. 502 hopewell junction, ny 12533-6531 tel: (800) powerpc fax: (800) powerfax sc09-3025-02

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